1. Technical Field
The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device allowing the charge sharing of data lines and a driving method thereof.
2. Description of the Related Art
A liquid crystal display device (LCD) displays an image corresponding to video data by controlling light transmittance of liquid crystal. As illustrated in FIG. 1, the LCD includes a liquid crystal panel 2, a gate driver 4, a data driver 6, and a timing controller 8. On the liquid crystal panel 2, a plurality of gate lines GL1 to GLn and a plurality of data lines DL1 to DLm are intersected with one another. The gate driver 4 drives the gate lines GL1 to GLn and the data driver 6 drives the data lines DL1 to DLm. The timing controller 8 generates gate control signals for controlling the gate driver 4 and data control signals for controlling the data driver 6.
Pixel regions are defined by the intersections of the gate lines GL1 to GLn and the data lines DL1 to DLm. Each of the pixel regions includes a pixel having a thin film transistor (TFT) MT, a liquid crystal cell CLc, and a storage capacitor Cst. The TFT MT has a gate electrode connected to the corresponding gate line GL and a source electrode connected to the corresponding to the data line. The liquid crystal cell CLc is connected between a drain electrode of the TFT MT and a common terminal Vcom. The storage capacitor Cst is connected between the drain electrode of the TFT MT and a previous gate line GLi−1. The storage capacitor Cst may be connected between the drain electrode of the TFT MT and the common terminal VCOM.
Pixels of the liquid crystal panel 2 may be driven in a frame inversion system, a line inversion system, or a dot inversion system. The frame inversion system may invert a polarity of a pixel data voltage supplied to the pixel when the frame is changed. The line inversion system may invert a polarity of a pixel data voltage supplied to the pixel according to the liquid crystal panel 2, that is, the gate line. The dot inversion system may supply a pixel data voltage opposite to a pixel data voltage to be supplied to a pixel adjacent to an arbitrary pixel. Also, the line inversion system and the dot inversion system may be used in combination with the frame inversion system that inverts the polarity of the pixel data voltage to be supplied to the pixel at each frame.
Among the three driving methods, the dot inversion system supplies an arbitrary pixel with a pixel data voltage with a polarity opposite to a pixel data voltage to be supplied to a pixel adjacent in a vertical or horizontal direction. Therefore, compared with the frame inversion system and the line inversion system, the dot inversion system can provide higher image quality. For this reason, the dot inversion system is widely used to drive the liquid crystal panel.
The dot inversion system is classified into a 1 dot-1 line inversion system in which a polarity of a pixel data voltage is inverted at each 1 dot, and a 1 dot-2 line inversion system in which a polarity of a pixel data voltage is inverted at each 2 dot. According to the 1 dot-2 line inversion system, as illustrated in FIGS. 2A and 2B, a polarity of a pixel data voltage is inverted at each 1 dot in a horizontal direction, while it is inverted at each 2 dot in a vertical direction. When the liquid crystal panel is driven at a frame frequency of 60 Hz (that is, when 60 images are displayed for 1 second), the 1 dot-2 line inversion system can reduce a flicker phenomenon compared with the 1 dot-1 line inversion system.
The LCD using the 1 dot-2 line inversion system has a charge sharing function that allows the data lines to share charges. The data driver 6 of the LCD with the charge sharing function includes m number of first switches SW1 to SW1-m connected between a plurality of buffers 10-1 to 10-m and a plurality of data lines DL1 to DLm, and (m−1) number of second switches SW2-1 to SW2-(m−1) connected between the plurality of data lines DL1 to DLm, as shown in FIG. 3. Each of the buffers 10 supplies analog pixel data voltage to the corresponding data line DL through the first switch SW1. The first switches SW1 and the second switches SW2 are complementarily turned on in response to a data output enable signal DOE, which is one of the data control signals supplied from the timing controller 8. When the data output enable signal DOE is high (or low), the first switches SW1 are turned on, while the second switches SW2 are turned off. On the contrary, when the data output enable signal DOE is low (or high), the first switches SW1 are turned off, while the second switches SW2 are turned on.
For example, when a scan signal is supplied to the first gate line GL1, the TFT MT connected thereto is turned on and the data output enable signal DOE is high. In this case, each of the buffers 10-1 to 10-m supplies an opposite pixel data voltage to the corresponding data line DL through the first switch SW1. Then, each of the TFTs MT connected to the first gate line GL1 charges the corresponding liquid crystal cell CLc and the corresponding storage capacitor Cst with the pixel data voltage applied on the corresponding data line DL.
On the contrary, when the data output enable signal DOE is low, the second switches SW2 instead of the first switches SW1 are turned on so that the data lines DL1 to DLm are connected to one another. Then, voltage charge/discharge are performed between the data lines DL charged with the pixel data voltages of the polarity opposite to that of the adjacent data lines DL. For example, when the odd data lines DL1, DL3, . . . , DLm−1 are charged with the pixel data voltage of a negative polarity and the even data lines DL2, DL4, . . . , DLm are charged with the pixel data voltage of a positive polarity, the odd data lines DL1, DL3, . . . , DLm−1 are charged with the voltage of the adjacent even data lines DL2, DL4, . . . , DLm, while the even data lines DL2, DL4, . . . , DLm discharge the charged pixel data voltage of the positive polarity to the adjacent odd data lines DL1, DL3, . . . , DLm−1. As a result, the charge sharing occurs so that all the data lines DL1 to DLm are pre-charged to a middle level of the pixel data voltage of the positive polarity and the pixel data voltage of the negative polarity. Due to the charge sharing exhibiting the pre-charge effect, the power consumption of the data driver (or further the LCD) can be reduced.
Like the waveforms of EGS-O and EGS-E in FIG. 4, such a charge sharing may be performed regardless of the polarity signal POL, every when the gate line GL is changed (that is, at each period of the horizontal sync signal) (hereinafter, referred to a “single-line sharing method”). Also, like the waveforms of EPE-O and EPE-E, the charge sharing may be performed at each edge of the polarity signal POL (that is, at every period of the 2 horizontal sync signals) (hereinafter, referred to as a “polarity edge sharing method”). EGS-O and EGS-E of FIG. 4 are waveforms in the single-line sharing method, explaining the pixel data voltages supplied to the odd data lines DL1, DL3, . . . , DLm−1, and the pixel data voltages supplied to the even data lines DL2, DL4, . . . , DLm. EPE-O and EPE-E of FIG. 4 are waveforms in the polarity edge sharing method, explaining the pixel data voltages supplied to the odd data lines DL1, DL3, . . . , DLm−1, and the pixel data voltages supplied to the even data lines DL2, DL4, . . . , DLm. In FIG. 4, POL represents the waveform of the polarity signal.
In the case of the single-line sharing method, however, the charge sharing is unnecessarily performed even when the pixel data voltages with the same polarity and same voltage level are consecutive. Thus, the power consumption cannot be reduced below a predetermined limit. Also, in the case of the polarity edge sharing method, a necessary charge sharing is not performed when the pixel data voltages with the same polarity but different voltage level are consecutive. Consequently, the power consumption cannot be reduced below a predetermined limit.